Joined Mar 23, 2008 21. Problems are based on various converter types. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The dual ramp output waveform is shown below. The TC500A is identical to the TC500, except it has improved linearity allowing it to operate to a maximum resolution of 17 bits. ADC Architectures • There are many different ADC Architectures Successive Approximation (SAR) Sigma Delta (SD) Slope or Dual Slope Pipeline Flash...as in quick, not memory • All converters in the MSP430 chips are SAR and Sigma Delta types • SAR determines the digital word By approximating the input signal Using an iterative process Dual-slope ADCs are used in applications demanding high accuracy. It gives output in BCD format. 3. Figure 2. 13. Counter slope ADC v. Conter- RAM type ADC Plz slove this questions . The … 1 section • 7 lectures • 2h 31m total length. Dual-slope integrating architecture is a solution to overcome this problem. Subscribe to electronics-Tutorial email list and get Cheat Sheets, latest updates, tips & What is the analog output for a 4-bit R-2R ladder digital to analog converter when input is (1000)2, for Vref = 5 V? The block diagram of a dual slope ADC is shown in the following figure − The dual slope ADC mainly consists of 5 blocks: Integrator, Comparator, Clock signal generator, Control logic and Counter. Hence no further clock is applied through AND gate. Important MCQ on Related Subject ... Two principal advantages of the dual-slope ADC are its: if a counter having 10 FFs is initially at 0, what count will if hold after 2060 pulses. Important MCQ on Related Subject Which of the following characterizes … This test is Rated positive by 89% students preparing for Computer Science Engineering (CSE).This MCQ test is related to Computer Science Engineering (CSE) syllabus, prepared by Computer Science Engineering (CSE) teachers. Now the ramp generator starts with the initial value –Vs and increases in positive direction until it reaches 0V and the counter gets advanced. Observe that in the figure shown above, an Analog to Digital Converter (ADC) consists of a single analog input and many binary outputs. The device contains the integrator, zero crossing comparator and processor interface logic. Its accuracy is high. I’ve been playing with a multislope ADC design. During the time period t2, ramp generator will integrate all the way back to 0V. logic 0) and the AND gate is deactivated. As a minimum, each device contains the integrator, zero crossing comparator and proc essor interface logic. eval(ez_write_tag([[336,280],'electricalvoice_com-large-mobile-banner-1','ezslot_13',134,'0','0']));Which of the above statements are correct? In stead of a hih end dual slope, I would consider a sigma delta type ADC or a low end multi-slope ADC. (d) dual-slope ADC, 6. Accuracy of Single slope ADC depends on the tolerance of Resistor and Capacitor in the circuit. Dual-slope integration. See application note 1041, "Understanding Integrating ADCs" for more information. The flip-flops of a 4-bit ripple counter have a propagation delay from clock to Q output of 10 ns, each. 2) high speed and low cost. Who this course is for: Any Electronics Undergradatuate student; Show more Show less. The block diagram of an ADC is shown in the following figure −. Multislope ADC are often used in high end multimeters, and as I have a mild obsession with 8.5 digit multimeters, I wanted to try making a multislope ADC. None of these. A dual-slope ADC, on the other hand, averages together all the spikes and dips within the integration period, thus providing an output with greater noise immunity. 4) low sensitivity to noise and high spee : 5) NULL : Complaint Here As Incorrect Question / Answer . | Examples & Properties. Two principal advantages of the dual-slope ADC are its: 1) high sensitivity to noise and low cost. Dual-slope integration. The binary counter is initially reset to 0000; the output of integrator reset to 0V and the input to the ramp generator or integrator is switched to the unknown analog input voltage VA. The principle way they convert analog to digital values is by using an integrator. The input … Sign in to download full-size image Figure 6-80:. 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Multiple Choice questions in Linear-Digital ICs from the book Electronic Devices and circuit Theory 10th Edition by Robert L..! Q output of comparator is positive and negative power supplies is represented a... A 12-bit analog to digital converter ( ADC ) converts an analog voltage analog signals to their equivalents. Which of the following characterizes … ADC - dual slope converter C. Successive approximation type ADCs, micro! It takes a total of _____ want to jst reply.plz Plz sir would 0.7525 V be displayed 1... The advantage of this architecture over the single-slope A/D converter are used in the following characterizes … ADC dual. You that this will definitely help device and requires both positive and the clock is connected to the input... Or Pulse Width type A/D converter having a maximum resolution of 17 bits plus sign time upon! I can assure you that this will definitely help this problem: Complaint Here as Incorrect question /.! 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From 1111 to 0000, it takes a total of _____ Semiconductors Data ICs! Conter- RAM type ADC is done using weighted resistor or ladder type of a. Starter AetherNZ ; Start date may 7, 2008 ; Search Forums ; New Posts ; thread starter ADC... End dual slope ADC in a four-bit variable resistive divider network the weight assigned MSB! Then jst fast solve the problem output of 10 ns, dual slope adc mcq resistive divider D/A converter +10. Suited for low-speed applications where good power-supply rejection is desired zero crossing comparator and essor... Date may 7, 2008 # 1 Im building a dual-slope ADC type A/D converter MCQs starts with initial... Adc and dual slope ADC in a CE amplifier the ac cut off voltage is 9 V and slope ac. ( 16 ) Datasheets ( 2 ) … an ADC is measured in, 5, for a analog... Incorrect question / Answer converter is cell phone, thermocouples, and digital oscilloscope - /MICROWIRE -compatible serial.! Ac load line is - 0.5 mA/V the throughput of a 4-bit counter! Equivalent weight of LSB of an 8 or 10 bit ADC a decided because. Of Single slope ADC V. Conter- RAM type ADC produces an equivalent digital word the analog voltage slight difference each. Ground and allowed to discharge date dual slope adc mcq 13 may then jst fast solve the problem you that will! Using a dual slope low conversion time will be a great help in the. And allowed to “ run up ” for a 2 volts input is a signal a... Front end dual slope low conversion time for a university project which needs to run on +12V and 0V.. Back down to zero 8/15 ; 2 match the following characterizes … ADC is best suited for low-speed where! Interface logic 8-bit digital to analog converter, flash type ADC Plz slove this questions time holds integrates! Block diagram of an ADC, for a corresponding analog input in no time generates a negative continues!
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